Abstract: A new technique isintroduced that combines the advantages of the output wired CMOS logic with themajority gate. The concept of majority gate is of utmost importance because ithelps in reducing the delay produced in the circuits and output wired CMOSlogic helps in reducing the transistor count. The adder circuits i.e. fulladder, ripple carry adder and carry look ahead adder have been simulated usingtanner tool for 130nm channel length.
The results obtained show that this newtechnique has an advantage of delay reduction and less power consumption ascompared to the conventional design. Also, the transistor count for the designsis less than the conventional design transistor count.Keywords – Adder, ComplementaryMetal Oxide Semiconductor (CMOS), full adder, Majority gate,ripple carry adder,carry look ahead adder I. IntroductionOne of the basic fundamentalarithmetic operation is addition. It is extensively used in applicationspecific systems. The adder cell designed is based on majority gate and outputwired CMOS logic.
It helps in dealing with issues of power consumption, delayin output, transistor count and the area required for the design. There are different implementationtechniques for threshold gate based logic design. Threshold gate can beimplemented using capacitive threshold logic , output wired CMOS inverter ,MOS-NDR based monostable bistable transistor logic .In this paper, we havedesigned one bit full adder CMOS circuit using output wired CMOS logic basedmajority gate.
Further, the other adder circuits i.e. 4-bit ripple carry adderand 2 bit carry look ahead adder circuit has been designed using the samelogic.
On performing the comparative analysis, the simulation results show thatthe proposed designs have less delay and reduced power consumption.Other sections in the paper include:Section II : Description of Concept of majority gateSection III :Discussing concept of output wired CMOS logicSection IV: Design of one bit full adder using output wired CMOS logic based majoritygateSection V: Design of ripple carry adder using output wired CMOS logic basedmajority gateSection VI: Design of carry look ahead adder using output wired CMOS logic based majoritygateSection VII : Comparison of proposed designs withconventional designsSection VIII: Conclusion. II. conceptof majority gateAmajority gate is a logical gate used in circuit complexity and other applicationsof Boolean circuits. In case of majority gate the output will be ‘1’ if overhalf of the inputs are ‘1’otherwise it will be ‘0’.
As shown in the figure 1,there are three inputs a, b and c and either of the two inputs are passedthrough the AND logic gate and the output obtained respectively are passedthrough the OR logic gate. Thus, the logic produced is: (1)Fig.1 3 input majority gateAsshown infig.2, the majority gate usually consists of odd number of inputs representedas “w”.Fig2 Majority gate functionIn other words, the majority gate can becalled a special case of threshold gate where the threshold value is equal tohalf of input plus one.
Mathematically, III. conceptof output wired logicA wired logic connection is a logic gate thatimplements Boolean algebra (logic) using only passive elements like resistors,capacitors. It also uses diode for the logic implementation when it’s notbehaving as an active device means when it has no negative differentialresistance. A wired logic connection can create an AND or OR gate.
Here,instead of AND and OR gate we have used CMOS as an element that helps to formthe output wired CMOS logic.