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       In this
section, performance analysis of decoder has been presented. All the simulations are performed on MICROWIND and DSCH (Digital
Schematic Editor and Simulator). For the reason that SPICE has three
built-in MOSFET models selected by the LEVEL parameter in the model card. The
LEVEL 1 SPICE model implements the shichman- Hodges models which is based on
the square law, it does not handle short-channel effects. The LEVEL 2 model is
geometry- based which uses detailed- device physics to define its equations. It
handles effects such as velocity saturation, mobility degradation and drain
induced barrier lowering. Unfortunately, including all 3D effects of an
advanced sub micron process in a pure physics based model becomes complex and
inaccurate. LEVEL 3 is a semi empirical model. It relies on mixture of
analytical and empirical expressions, and its uses measure device data to
determine its main parameters. It works quite well for channel lengths down to
1µm. accordingly the confusing situation of having to use a different model for
each manufacturer has fortunately been partially resolved by the adoption of
the BSIM 3 model as an industry wide standard for the modelling of deep-sub
micron MOSFET transistors. The Berkeley short-channel model provides a model
that is analytically simple and is based on a ‘small ‘on number of parameters,
which normally are extracted empirical data. Its popularity and accuracy make
it the natural choice. A full-fledged BSIM 3 model contain over 200 parameters
the majority  of which are related to the
modelling of second order effects. The MICROWIND2 program allows the student to
design and simulate an integrated circuit at physical description level. The
package contains a library of common logic and analog ICs to view and simulate.
The DSCH2 program is a logic editor and simulator. DSCH2 is used to validate
the architecture of the logic circuit before the microelectronics design is
started. DSCH2 provides a user friendly environment for hierarchical logic
design, and simulation with delay analysis, which allows the design and
validation of complex logic structures. A key innovative feature is the
possibility to estimate the power consumption of the circuit. The main focus of this work is to reduce
the transistor count by adopting mixed logic topology, thereby lowering the
power requirements compared to single-style design. The simulation results are
shown below Figures.

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