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       In thissection, performance analysis of decoder has been presented. All the simulations are performed on MICROWIND and DSCH (DigitalSchematic Editor and Simulator). For the reason that SPICE has threebuilt-in MOSFET models selected by the LEVEL parameter in the model card.

TheLEVEL 1 SPICE model implements the shichman- Hodges models which is based onthe square law, it does not handle short-channel effects. The LEVEL 2 model isgeometry- based which uses detailed- device physics to define its equations. Ithandles effects such as velocity saturation, mobility degradation and draininduced barrier lowering. Unfortunately, including all 3D effects of anadvanced sub micron process in a pure physics based model becomes complex andinaccurate. LEVEL 3 is a semi empirical model. It relies on mixture ofanalytical and empirical expressions, and its uses measure device data todetermine its main parameters. It works quite well for channel lengths down to1µm.

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accordingly the confusing situation of having to use a different model foreach manufacturer has fortunately been partially resolved by the adoption ofthe BSIM 3 model as an industry wide standard for the modelling of deep-submicron MOSFET transistors. The Berkeley short-channel model provides a modelthat is analytically simple and is based on a ‘small ‘on number of parameters,which normally are extracted empirical data. Its popularity and accuracy makeit the natural choice. A full-fledged BSIM 3 model contain over 200 parametersthe majority  of which are related to themodelling of second order effects. The MICROWIND2 program allows the student todesign and simulate an integrated circuit at physical description level. Thepackage contains a library of common logic and analog ICs to view and simulate.The DSCH2 program is a logic editor and simulator.

DSCH2 is used to validatethe architecture of the logic circuit before the microelectronics design isstarted. DSCH2 provides a user friendly environment for hierarchical logicdesign, and simulation with delay analysis, which allows the design andvalidation of complex logic structures. A key innovative feature is thepossibility to estimate the power consumption of the circuit. The main focus of this work is to reducethe transistor count by adopting mixed logic topology, thereby lowering thepower requirements compared to single-style design. The simulation results areshown below Figures.

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